1. Field of the Invention
The present invention relates to nonvolatile memory and integrated circuits including such memory, and more particularly to architectures for such devices supporting the storage of data on the use of the nonvolatile memory.
2. Description of Related Art
Electrically programmable and erasable nonvolatile memory technologies, such as flash memory and charge trapping memory, have many applications. Technologies based on floating gates, like EEPROM, and localized charge trapping structures like oxide-nitride-oxide memory cells known in various architectures as SONOS cells and NROM, are typically programmable and erasable many times.
The operating characteristics of nonvolatile memory cells change over the lifetime of the nonvolatile memory cells. As nonvolatile memory cells undergo an increasing number of program and erase cycles, the operational characteristics of the nonvolatile memory cells change. This aspect of nonvolatile memory technologies is problematic, because nonvolatile memory cells are expected to operate predictably over their expected lifetimes, regardless of the number of program and erase cycles any particular nonvolatile memory cell has experienced.
One approach to the varying behavior of nonvolatile memory cells due to an increasing number of program and erase cycles is rely exclusively on appropriate margins determined from the beginning, such that even if the operational characteristics of the nonvolatile memory cells change with an increasing number of program and erase cycles, the operating margins account for any expected varying behavior of the nonvolatile memory cells within the specified lifetime of the nonvolatile memory cells. However, exclusively relying on appropriately determined margins may subject nonvolatile memory cells to unnecessarily extreme operating conditions during part of their lifetimes. Such operating margins impliedly are more stringent than required during at least some portion of the lifetime of a nonvolatile memory cell. During this portion of the lifetime of some nonvolatile memory cells, the unnecessarily extreme operating conditions tend to shorten the lifetime of the nonvolatile memory cells.
Another approach to the varying behavior of nonvolatile memory cells due to an increasing number of program and erase cycles is rely exclusively on specifying a shorter lifetime for the nonvolatile memory cells. Although specifying a shorter lifetime is a simple solution, users of the nonvolatile memory cells must then more frequently replace the nonvolatile memory cells, as the increasing number of program and erase cycles undergone by the nonvolatile memory cells approaches the shorter lifetime. If replacing just the nonvolatile memory cells is impractical or not cost-effective, then the entire product which includes the nonvolatile memory cells is discarded or replaced.
Accordingly, it is desirable to provide apparatuses and methods for accounting for the operational characteristics of nonvolatile memory cells which vary with an increasing number of program and erase cycles over the lifetime of the nonvolatile memory cells.